In the prior art, overhead bytes, such as J1/B3/C2/G1/H4/K3, which are used to ensure normal transmission of high-order path VC-4/STS-1 SPE, will be processed in mapping chip and low-order cross chip in a Synchronous Digital Hierarchy (SDH)/Synchronous Optical Network (SONET) overhead processing equipment. J1 byte is used to ensure path continuous transmission, B3 byte is used to check if there is an error bit in a path, C2 byte is used to ensure that a signal type is right, G1 is used to acknowledge receipt of a remote error bit alarm, H4 is used for indication of low-order path multi-frames, and K3 is used for APS protection shift among VC-4 high-order paths.
A conventional implementing method is to process an overhead byte when a corresponding time slot arrives, then generate a corresponding alarm and report to a micro-processor. Generally speaking, overhead byte processing and arrival of overhead time slot are closely interrelated, and an overhead byte is processed immediately when an overhead time slot arrives.
One processing manner of prior art is that the number of overhead processing logics should be equal to the number of overheads such as High-order path Overhead (HPOH). So for an instance application of 4×622M, 16 overhead processing logics are required to be instantiated, as shown in FIG. 1. The overhead processing logics are provided correspondingly without multiplexing, which results in increased area of chips and higher power consumption. Accordingly, the manufacturing cost of chips rises sharply, and overhead processing of large scale chips, such as 10 G, 40 G chips, can not be achieved.
Another processing method of prior art is to achieve certain degree of multiplexing, as shown in FIG. 2. Still take an application of 4×622M as an example, if the work clock of the chip is 77.76 MHz, the chip will multiplex the overhead processing logics in unit of 622M, or 8×77.76 MHz parallel data, i.e., four VC-4s use a set of overhead processing logic in common. A memory is used to store middle results, and the integration of the entire logics and the memory will be instantiated four times, thus accomplishing overhead processing logics with a capacity of 2.5 G. Although certain degree of overhead processing logic multiplexing is adopted in the implementing method, the restriction to the system clock frequency still can not be overcome. For the 8×77.76 MHz parallel data, only four VC-4s can be multiplexed, and for the 8×77.76 MHz parallel data, only eight VC-4s high-order overhead processing can be multiplexed. Since the work clock of the chip can not be increased unlimitedly, the overhead processing of large capacity chips such as 20 G(128 VC-4), 40 G(256 VC-4) chips, will also result in increased area of chips, increased power consumption, and accordingly the manufacturing cost of the chip will be increased.
Therefore, there exists some defects in the prior art, and improvements and developments are required.